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1

Tony wrote:

  Providing that there's a way to get a bunch of cheapo CPUs to do the
  job.

True, but there's a complexity hit (which translates into a reliability hit
and a development lag) from this approach.

Well, i do not think that using off-the-shelf cheapo CPUs debugged by
somebody else and tested in millions of applications, instead of
single-purpose ASICs qualifies as a reliability hit or a development lag :slight_smile:

--vadim

2

Well, i do not think that using off-the-shelf cheapo CPUs debugged by
   somebody else and tested in millions of applications, instead of
   single-purpose ASICs qualifies as a reliability hit or a development lag :slight_smile:

Agreed that the part itself is correct. However, unlike you, the rest of
us tend to take perfect parts and make mistakes putting them together. :wink:

Tony